GMS and EDGE base stations require PLL synthesizers that can frequency hop over the full transmit or receive band (e.g., 75 MHz) in less than about 10 μs and also have very low phase noise and spurious tones. Conventional designs typically overcome these conflicting requirements with a “ping-pong” architecture which utilizes two narrow bandwidth PLLs wherein one PLL is locking to the next desired frequency while the other PLL is active as the synthesizer for the current burst. However, the ping-pong type design requires two PLL chips, two high performance VCOs and about 100 dB of isolation between the PLLs which is expensive and bulky.
Examples of fast locking PLLs which attempt to overcome the problems associated with the ping-pong type architecture are disclosed in U.S. Pat. Nos. 4,156,855 and 5,420,545, both incorporated by reference herein. The '855 and the '545 patents disclose fast locking PLLs where the bandwidth is increased to speed up the lock time by increasing the charge pump current and at the same time a switch is closed to short out part of the loop filter zero resistance. Increasing the charge pump current by a factor of N while reducing the loop filter resistance by √{square root over (N)} increases the loop bandwidth by √{square root over (N)} while leaving the phase margin unchanged. For example, to increase the loop bandwidth by a factor of 8 for wide bandwidth mode, the charge pump current may be increased by a factor of 64 while the loop filter resistance is decreased by a factor of 8. Similarly, to decrease the loop bandwidth to narrow bandwidth mode, the charge pump current may be reduced by a factor of 64 while the loop filter resistance is increased by a factor of 8. In these prior art designs, when the PLL has locked or is close to lock, the loop bandwidth is reduced again to reduce phase noise and spurious by reducing the charge pump current to the charge pump's minimum value and simultaneously opening the loop filter switch to increase the zero resistance again to restore the phase margin. These prior art designs all suffer from an excessively large disturbance to the frequency and phase settling transients when the bandwidth is reduced. This disturbance takes a long time to settle out since the bandwidth is reduced and the loop time constants have increased. The major cause of this disturbance is that the current flowing in the loop filter resistor can still be large when the loop filter resistance is increased. This is particularly the case with a fractional-N PLL which settles with an average phase error of zero but with an instantaneous error at the PFD that may have peak deviations up to ±4 RF periods. This gives rise to significant current pulses through the loop filter resistor. If the resistance is increased while current is flowing through the loop filter there will be a corresponding voltage increase seen across the resistor. This voltage step will appear on the VCO tuning voltage and the result is that excessive phase disturbance is generated and an output phase shift occurs which is greater than the ±5° limits required for GMS and EDGE applications.
Moreover, the '545 patent discloses that the reference and feedback divider values are also changed when the loop reverts from wide bandwidth to narrow bandwidth modes. The phase change associated with this technique takes an excessively long time to settle out when the loop is in narrow bandwidth mode.